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| a FEATURES Excellent Gain Accuracy: 0.99 V/V Wide Bandwidth: 750 MHz Slew Rate: 1200 V/ s Low Distortion -65 dBc @ 20 MHz -80 dBc @ 4.3 MHz Settling Time 5 ns to 0.1% 8 ns to 0.02% Low Noise: 2.4 nV/Hz Improved Source for CLC-110 APPLICATIONS IF/Communications Impedance Transformations Drives Flash ADCs Line Driving Low Distortion 750 MHz Closed-Loop Buffer Amp AD9630* PIN CONFIGURATION +VS 1 ** 2 NC 3 INPUT 4 8 OUTPUT 7 NC 6 *** AD9630 5 -VS NC = NO CONNECT **OPTIONAL +VS ***OPTIONAL -VS NOTE: FOR BEST SETTLING TIME PERFORMANCE USE OPTIONAL POWER SUPPLIES. ALL SPECIFICATIONS ARE BASED ON USING SINGLE VS CONNECTIONS, EXCEPT FOR SETTLING TIME TO 0.02% AND SMALL SIGNAL S21. CONSULT THE FACTORY FOR VERSIONS WITH OPTIONAL POWER SUPPLY PINS DISCONNECTED INTERNAL TO THE PACKAGE. GENERAL DESCRIPTION The AD9630 is a monolithic buffer amplifier that utilizes a patented, innovative, closed-loop design technique to achieve exceptional gain accuracy, wide bandwidth, and low distortion. Slew rate limiting has been overcome as indicated by the 1200 V/s slew rate; this improvement allows the user greater flexibility in wideband and pulse applications. The second harmonic distortion terms for an analog input tone of 4.3 MHz and 20 MHz are -80 dBc and -66 dBc, respectively. Clearly, the AD9630 establishes a new standard by combining outstanding dc and dynamic performance in one part. The large signal bandwidth, low distortion over frequency, and drive capabilities of the AD9630 make the buffer an ideal flash ADC driver. The AD9630 provides better signal fidelity than many of the flash ADCs that it has been designed to drive. Other applications that require increased current drive at unity voltage gain (such as cable driving) benefit from the AD9630's performance. The AD9630 is available in plastic DIP (N) and SOIC (R). *Protected under U.S. patent numbers 5,150,074 and 5,537,079. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 (c) Analog Devices, Inc., 1999 AD9630-SPECIFICATIONS ELECTRICAL CHARACTERISTICS (unless otherwise noted, Parameter DC SPECIFICATIONS Output Offset Voltage Offset Voltage TC Input Bias Current Bias Current TC Input Resistance Input Capacitance Gain Output Voltage Range Output Current (50 Load) Output Impedance PSRR DC Nonlinearity FREQUENCY DOMAIN Bandwidth (-3 dB) Small Signal Large Signal Output Peaking Output Rolloff Group Delay Linear Phase Deviation 2nd Harmonic Distortion At DC VS = 5% 2 V Full Scale Conditions Temp +25C Full +25C Full +25 to T MAX TMIN +25C +25 to T MAX TMIN Full +25 to T MAX TMIN +25C Full +25C VS = 5 V; RIN = 50 Test Level I IV I IV II VI V II VI VI II VI V VI V , RLOAD = 100 Min ) Units mV V/C A nA/C k k pF V/V V/V V mA mA dB % AD9630AN/AR Typ Max 3 8 2 20 450 250 1.0 0.990 0.985 3.6 +8 +40 +25 +100 -8 -40 -25 -100 300 150 0.983 0.980 +3.2 50 40 44 VOUT = 2 V p-p VOUT = 2 V p-p -3.2 0.6 55 0.03 3rd Harmonic Distortion Spectral Input Noise Voltage Integrated Output Noise TIME DOMAIN Slew Rate Rise/Fall Time VO 0.7 V p-p VO 0.7 V p-p VO = 5 V p-p VO = 5 V p-p 200 MHz 200 MHz DC to 150 MHz DC to 150 MHz 2 V p-p; 4.3 MHz 2 V p-p; 20 MHz 2 V p-p; 50 MHz 2 V p-p; 4.3 MHz 2 V p-p; 20 MHz 2 V p-p; 50 MHz 2 V p-p; 50 MHz 10 MHz 100 kHz - 200 MHz VOUT = 5 V Step VOUT = 1 V Step VOUT = 1 V Step VOUT = 5 V Step VOUT = 5 V Step VOUT = 2 V Step VOUT = 2 V Step VOUT = 2 V Step VOUT = 2 V Step VOUT = 2 V Step 4.4 MHz 4.4 MHz VCC = +5 V VEE = -5 V TMIN to +25 TMAX TMIN to +25 TMAX Full Full +25C +25C Full Full Full Full Full TMIN to +25 TMAX +25C +25C +25C +25C TMIN to T MAX +25C TMIN to T MAX Full TMIN to +25 TMAX TMIN to +25 TMAX +25C +25C Full Full II II V V II II V V IV IV II IV IV II II V V IV IV IV IV IV IV IV IV IV V V V II II 400 330 750 550 120 105 0.4 0 0.7 0.7 -80 -66 -52 -86 -75 -47 -46 2.4 32 1200 1.1 1.3 4.2 5.0 2 6 7 8 12 0.015 0.025 19 19 1.2 0.3 -73 -58 -43 -79 -68 -41 -40 MHz MHz MHz MHz dB dB ns Degrees dBc dBc dBc dBc dBc dBc dBc nV/Hz V V/s ns ns ns ns % ns ns ns ns % Degree mA mA 700 Overshoot Amplitude Settling Time To 0.1% To 0.02%4 Differential Gain Differential Phase SUPPLY CURRENTS VCC (+IS) VEE (-I S) 1.7 1.9 5.7 6.5 12 10 12 26 26 NOTES 1 Short-term settling with 50 source impedance. Specifications subject to change without notice. -2- REV. B AD9630 ABSOLUTE MAXIMUM RATINGS 1 Supply Voltages ( VS) . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Continuous Output Current2 . . . . . . . . . . . . . . . . . . . . . 70 mA Temperature Range over Which Specifications Apply AD9630AN/AR . . . . . . . . . . . . . . . . . . . . . -40C to +85C Lead Soldering Temperature (10 sec) . . . . . . . . . . . . . +300C Storage Temperature AD9630AN/AR . . . . . . . . . . . . . . . . . . . . -65C to +150C Junction Temperature3 AD9630AN/AR . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150C NOTES 1 Absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2 Output is short-circuit protected to ground, but not to supplies. Prolonged short circuit to ground may affect device reliability. 3 Typical thermal impedances (part soldered onto board): Plastic DIP (N): JA = 110C/W; JC = 30C/W; SOIC (R): JA = 155C/W; JC = 40C/W. EXPLANATION OF TEST LEVELS Test Level I 100% Production tested. II 100% Production tested at +25C and sample tested at specified temperatures. AC testing of AN and AR grades done on sample basis only. III Sample tested only. IV Parameter is guaranteed by design and characterization testing. V Typical value. VI S Versions are 100% production tested at temperature extremes. Other grades are sample tested at extremes. 100 (5%, 0.25W) +5V 0.1 F 1 8 AD9630 7 NC NC 2 TOP VIEW NC 3 (Not to Scale) 6 NC 4 5 0.1 F NC = NO CONNECT -5.2V ORDERING GUIDE Temperature Range Package Description Package Option 24 (5%, 0.25W) Model AD9630 Burn-In Circuit AD9630AN -40C to +85C 8-Lead Plastic DIP N-8 AD9630AR -40C to +85C 8-Lead SOIC SO-8 AD9630AR-REEL -40C to +85C 13" Tape and Reel SO-8 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9630 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE THEORY OF OPERATION The AD9630 is a wide-bandwidth, closed-loop, unity-gain buffer that makes use of a new voltage-feedback architecture. This architecture brings together wide bandwidth and high slew rate along with exceptional dc linearity. Most previous widebandwidth buffers achieved their bandwidth by utilizing an open-loop topology which sacrificed both dc linearity and frequency distortion when driven into low load impedances. The design's high loop correction factor radically improves dc linearity and distortion characteristics without diminishing bandwidth. This, in combination with high slew rate, results in exceptionally low distortion over a wide frequency range. The AD9630 is an excellent choice to drive high speed and high resolution analog-to-digital converters. Its output stage is designed to drive high speed flash converters with minimal or no series resistance. A current booster built into the output driver helps to maintain low distortion. Parasitic or load capacitance (>7 pF) connected directly to the AD9630 output will result in frequency peaking. A small series resistor (RS) connected between the buffer output and capacitive load will negate this effect. Figure 1 shows the optimal value of RS as a function of CL to obtain the flattest frequency response. Figure 2 illustrates frequency response for various capacitive loads utilizing the recommended RS. 50 RS 40 200 "R" CL RSERIES - 30 20 NO RS NEEDED WHEN CL < 7pF; FOR CL > 30pF, "R" CAN BE OMITTED 0 10 0 7 20 40 CL - pF 60 80 100 Figure 1. Recommended RS vs. CL REV. B -3- AD9630 2 1 FREQUENCY RESPONSE - dB 0 -1 -2 -3 -4 -5 -6 -7 -8 <0.1MHz 50pF 10pF 25pF the device output. To avoid this occurrence, the power supply leads should be tightly twisted (if appropriate). Ferrite beads mounted between the tantalum and ceramic capacitors will serve the same purpose. All unused pins (except the optional power supply pins) should be connected to ground to reduce pin-to-pin capacitive coupling and prevent external RF interference. If the source and drive electronics require "remote" operation (> 1 inch from the AD9630), the PC board line impedances should be matched with the buffer input and output resistances. Basic microstrip techniques should be observed. RIN and RS should be connected as close to the AD9630 as possible. 100MHz CL 200MHz 300MHz Figure 2. Frequency Response vs. C L with Recommended RS With only minimal pulse overshoot and ringing, the AD9630 can drive terminated cables directly without the use of an output termination resistor (RS). Termination resistors (RS and R IN) can be either standard carbon composition or microwave type. For matching characteristic impedances, precision microwave resistors of 1% or better tolerance are preferred. The AD9630 should be soldered directly to the PC board with as little vertical clearance as possible. The use of zero insertion sockets is strongly discouraged because of the high effective pin inductances. Use of this type socket will result in peaking and possibly induce oscillation. +VS 4.7 F In pulse mode applications, with RS equal to approximately 12 , capacitive loads of up to 50 pF can be driven with minimal settling time degradation. The output stage has short circuit protection to ground. The output driver will shut down if more than approximately 130 mA of instantaneous sink or source current is reached. This level of current ensures that output clipping will not result when driving heavy capacitive loads during high slew conditions, although average load currents above 70 mA may reduce device reliability. LAYOUT CONSIDERATIONS 0.1 F 0.1 F Due to the high frequency operation of the AD9630 attention to board layout is necessary to achieve optimum dynamic performance. A two ounce copper ground plane on the top side of the board is recommended; it should cover as much of the board as possible with appropriate openings for supply decoupling capacitors as well as for load and source termination resistors, (see Figure 3). Optimum settling time and ac performance results will be achieved with surface mount 0.1 F supply decoupling ceramic chip capacitors mounted within 50 mils of the corresponding device pins with the other side soldered directly to the ground plane. For best high resolution (<0.02%) settling times, the optional power supply pins should be decoupled as shown above. If the optional power supply pins are not used, they should be left open. If surface mount capacitors cannot be used, radial lead ceramic capacitors with leads less than 30 mils long are recommended. Low frequency power supply decoupling is necessary and can be accomplished with 4.7 F tantalum capacitors mounted within 0.5 inches of the supply pins. Due to the series inductance of these capacitors interacting with the 0.1 F capacitors and power supply leads, high frequency oscillations might appear on 1 2* VIN RIN RS** 8 AD9630 6* 5 VOUT 0.1 F 0.1 F 4.7 F -VS *SEE PINOUTS **SEE FIGURE 1 Figure 3. AD9630 Application Circuit -4- REV. B Typical Performance Curves - AD9630 0 -100 -200 -300 -400 ppm -500 -600 -700 -800 -900 -1000 -3 1 -2 -1 0 VOLTS 1 2 3 1M 10M 100M FREQUENCY - Hz 1G 0 1M 10M 100M FREQUENCY - Hz 1G 100 10 10 5 20 0 RL = 100 RL = 200 100k 10k 1k 25 20 80 60 40 1M 30 100 |Zo| 15 Figure 4. Endpoint DC Linearity Figure 5. Input Impedance Figure 6. Output Impedance 50 50 50 50 OFFSET VOLTAGE - mV 10 8 6 TEST CIRCUIT 4 BIAS CURRENT 2 0 -2 -4 -6 -8 OFFSET VOLTAGE 50 40 30 20 10 0 -10 -20 -30 -40 25 CASE TEMPERATURE - C -50 125 BIAS CURRENT - A 40 INTERCEPT - +dBm 40 PSRR - dB 30 30 20 20 10 10 0 1M 100M 10M FREQUENCY - Hz 1G 0 dc 50 100 150 200 FREQUENCY - MHz 250 -10 -55 Figure 7. PSRR vs. Frequency Figure 8. 2-Tone Intermodulation Distortion Figure 9. Offset Voltage and Bias Current vs. Temperature 2 1 0 VIN = 100mV 3 2 1 RL = 200 0.25 RL = 50 VOLTS RL = 100 0.5 MAGNITUDE - dB GAIN 0 PHASE - Degrees MAGNITUDE - dB -1 -2 -3 -4 -5 -6 -7 -8 0M VIN = 750mV 0 -1 -2 -3 -4 -5 -6 PHASE VIN = 100mV -45 -90 -135 -180 0 TEST CIRCUIT 50 50 -0.5 6pF -0.25 200M 400M 600M 800M FREQUENCY - Hz 1G -7 0 40 80 120 160 FREQUENCY - MHz 200 2ns/DIVISION Figure 10 . Forward Gain and Phase Figure 11. Frequency Response vs. RLOAD Figure 12. Small-Signal Pulse Response REV. B -5- PHASE - Degrees - |Zo| AD9630 0.1 0.08 SETTLING PERCENTAGE - % 0.1 3.0 TEST CIRCUIT 2.5 2.0 100 0.04 0.02 0 -0.02 -0.04 -0.06 -0.08 VOUT = 2V STEP 1 10 100 1k TIME - ns 10k 100k VOLTS 6pF 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 5ns/DIVISION -0.1 TEST CIRCUIT 50 50 6pF TEST CIRCUIT SETTLING PERCENTAGE - % 0.08 0.06 0.06 100 0.04 0.02 0 -0.02 -0.04 -0.06 -0.08 -0.1 10 VOUT = 2V STEP 20 30 TIME - ns 40 50 6pF Figure 13. Short-Term Settling Time Figure 14. Long-Term Settling Time Figure 15. Large-Signal Pulse Response 40 RL = 100 50 2nd 60 dBc dBc 70 80 90 100 1 10 FREQUENCY - MHz 100 3rd 40 RL = 100 50 60 2nd 70 3rd 80 90 100 1 10 FREQUENCY - MHz 100 Figure 16. Harmonic Distortion VOUT = 4 V p-p Figure 17. Harmonic Distortion VOUT = 2 V p-p -6- REV. B AD9630 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 0.430 (10.92) 0.348 (8.84) 8 5 0.1968 (5.00) 0.1890 (4.80) 0.280 (7.11) 0.240 (6.10) 0.325 (8.25) 0.300 (7.62) 0.060 (1.52) 0.015 (0.38) 0.130 (3.30) MIN 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) 8 5 4 1 4 0.1574 (4.00) 0.1497 (3.80) PIN 1 1 0.2440 (6.20) 0.2284 (5.80) PIN 1 0.100 (2.54) BSC 0.210 (5.33) MAX 0.160 (4.06) 0.115 (2.93) 0.0500 (1.27) BSC 0.0098 (0.25) 0.0040 (0.10) SEATING PLANE 0.0688 (1.75) 0.0532 (1.35) 0.0192 (0.49) 0.0138 (0.35) 8 0.0098 (0.25) 0 0.0075 (0.19) 0.0196 (0.50) 0.0099 (0.25) 45 0.0500 (1.27) 0.0160 (0.41) 0.022 (0.558) 0.070 (1.77) SEATING 0.014 (0.356) 0.045 (1.15) PLANE REV. B -7- PRINTED IN U.S.A. C1401a-0-12/99 (rev. B) 8-Lead Plastic DIP (N-8) 8-Lead SOIC (SO-8) |
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